Our Mission

    Our mission is to bring to the world better, simpler, and more accessible methods of designing digital logic by promoting the evolution of the open standard TL-X language extensions.

 

    Exponential growth in chip complexities is making chip design a very costly proposition. Standards driven by big corporate interests tend to evolve as layers on top of layers, only adding to the complexity problem. It is time to replace old methods with cleaner, more powerful, and more community-minded ones. TL-X.org calls for folks across the industry to come together to work toward better solutions suitable to today's challenges.

 

 

    Most TL-X activities are now driven by Redwood EDA and through the Chip Design in Eastern MA meetup. TL-X.org remains the keeper of the TL-X specification. Feel free to join in any case, and we'll get you hooked up with the right activities.

 

 

What's TL-X?

    TL-X is a set of HDL (Hardware Description Language) features defined as extensions to existing HDL languages, including Verilog (as "TL-Verilog"), VHDL (as "TL-VHDL"), and SystemC (as "TL-C"). ("TL-Chisel is in the works.) Only TL-Verilog tools are currently available.

    TL-X is based on an open-source technology from Intel Corporation. The open source tool is now called TLV-Comp.

    TL-X Version 1a supports "timing abstraction" or pipelining as a fundamental language construct. Pipelines provide context for sequential logic. TL-X eliminates the need to code sequential elements, such as flip-flops, explicitly. Logic pipelining remains under designer control but can be easily and safely modified to meet cycle-time targets for a particular implementation of a design, even for logic you might not think of as pipelined. Generally, high-speed designs are less than half the size in TL-Verilog versus SystemVerilog without any loss in detail!
    TL-X 1 also supports state, "validity", and hierarchy, all very powerful capabilities.

    TL-X.org is currently nailing down TL-X Version 2a, which adds support for transactions, enabling high-level modeling and a top-down design methodology where high-level models can be evolved into production RTL.

    For details, see the documentation.

    Several other revolutionary design capabilities are on the horizon. You can be a part of their definition.

 

 

Who We Are

    TL-X.org (Transaction-Level eXtensions Organization) is an interest group, based in Massachusetts, with contributors from academia, industry, and the open-source community. We invite your participation. Our diversity is our strength.

 

 

What We Do

    TL-X.org coordinates the evolution of the open standard "TL-X" Transaction-Level hardware language extensions and fosters interest and adoption. We develop and maintain language specifications and coordinate the activities of various contributors to keep activities on a common course. Most contributions today are associated with Redwood EDA and the Chip Design in Eastern MA Meetup. Sign up to help define the future.

 

 

What We've Done

    Since our inception in late 2014, we have published several revisions of the TL-X spec and have helped introduce revolutionary capabilities into the design process. But, we're doing much more than creating documents. Already, TL-X has helped to inspire a TL-Verilog ecosystem with all the capabilities you need to write and develop in TL-X using these industry and open-source tools.

 

 

Sign Up

    Sign up using the link in the header of this page. Or contact us. We look forward to your participation!

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