Our mission is to bring to the world better, simpler, and more accessible methods of designing digital logic by promoting the evolution of the open standard TL-X language extensions.
Exponential growth in chip complexities is making chip design a very costly proposition. Standards driven by big corporate interests tend to evolve as layers on top of layers, only adding to the complexity problem. It is time to replace old methods with cleaner, more powerful, and more community-minded ones. TL-X.org calls for folks across the industry to come together to work toward better solutions suitable to today's challenges.
TL-X is a set of HDL (Hardware Description Language) features defined as extensions to existing HDL languages, including Verilog (as "TL-Verilog"), VHDL (as "TL-VHDL"), and SystemC (as "TL-C"). ("TL-Chisel, TL-Clash, etc. are also possible.) Only TL-Verilog tools are currently available.
TL-X is based on an open-source technology from Intel Corporation. The open source tool is now called TLV-Comp.
TL-X Version 1a supports "timing abstraction" or pipelining as a fundamental language construct. Pipelines provide context for sequential logic. TL-X eliminates the need to code sequential elements, such as flip-flops, explicitly. Logic pipelining remains under designer control but can be easily and safely modified to meet cycle-time targets for a particular implementation of a design, even for logic you might not think of as pipelined. Generally, high-speed designs are less than half the size in TL-Verilog versus SystemVerilog without any loss in detail!
TL-X 1 also supports state, "validity", and hierarchy, all very powerful capabilities.
TL-X.org is currently nailing down TL-X Version 2a, which adds support for transactions, enabling high-level modeling and a top-down design methodology where high-level models can be evolved into production RTL.
For details, see the documentation.
Several other revolutionary design capabilities are on the horizon. You can be a part of their definition.
Who We Are
TL-X.org (Transaction-Level eXtensions Organization) is, or was, an interest group, based in Massachusetts, with contributors from academia, industry, and the open-source community. Since our inception in late 2014, we have published several revisions of the TL-X spec and have helped introduce revolutionary capabilities into the design process. We've fostered open-source contributions to tools, such as editor modes for TL-Verilog.
Momentum has spread, and at this point, the effort is global and virtual. This site remains the keeper of the TL-X specification. Commercially, this work has become Redwood EDA, Open efforts are now primarily conducted within the TL-Verilog User's Slack Workspace.
How To Be a Part of It
Ample training resources are provided by Redwood EDA, and Makerchip.com is also a great place to start. Once you have become comfortable with TL-Verilog through available resources, feel free to join the conversation in the TL-Verilog User's Slack Workspace and introduce yourself in the #introductions channel. Folks interested in projects might consider the ones here.